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ltc2655 1 2655f block diagram features description quad i 2 c 16-/12-bit rail-to-rail dacs with 10ppm/c max reference the ltc ? 2655 is a family of quad i 2 c 16-/12-bit rail-to- rail dacs with integrated 10ppm/c max reference. the dacs have built-in high performance, rail-to-rail, output buffers and are guaranteed monotonic. the ltc2655-l has a full-scale output of 2.5v with the integrated refer- ence and operates from a single 2.7v to 5.5v supply. the ltc2655-h has a full-scale output of 4.096v with the integrated reference and operates from a 4.5v to 5.5v supply. each dac can also operate with an external reference, which sets the full-scale output to 2 times the external reference voltage. the parts use the 2-wire i 2 c compatible serial interface. the ltc2655 operates in both the standard mode (maxi- mum clock rate of 100khz) and the fast mode (maximum clock rate of 400khz). the ltc2655 incorporates a power-on reset circuit that is controlled by the porsel pin. if porsel is tied to gnd the dacs power-on reset to zero-scale. if porsel is tied to v cc , the dacs power-on reset to mid-scale.l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5396245, 6891433 and 7671770. inl curve applications n integrated reference 10ppm/c max n maximum inl error: 4lsb at 16 bits n guaranteed monotonic over temperature n selectable internal or external reference n 2.7v to 5.5v supply range (ltc2655-l) n integrated reference buffers n ultralow crosstalk between dacs (<1nv?s) n power-on-reset to zero-scale/mid-scale n asynchronous dac update pin n tiny 20-lead 4mm 4mm qfn and 16-lead narrow ssop packages n mobile communications n process control and industrial automation n instrumentation n automatic test equipment n automotive 2655 bd gndv outa v outb scl ca2ldac reflo ca1 ca0 refin/out refcomp v cc v outd v outc porsel sda internal reference dac a power-on reset dac b dac d dac c register 32-bit shift register 2-wire interface register register register register register register register code 128 inl (lsb) 4 C2 C1C3 2 31 0 C4 32768 49152 16384 2655 ta01b 65535 v cc = 5v downloaded from: http:///
ltc2655 2 2655f absolute maximum ratings supply voltage (v cc ) ................................... C0.3v to 6v scl, sda, ldac , reflo .............................. C0.3v to 6v v outa to v outd ................C0.3v to min (v cc + 0.3v, 6v) refin/out, refcomp .....C0.3v to min (v cc + 0.3v, 6v) porsel, ca0, ca1, ca2 ..C0.3v to min (v cc + 0.3v, 6v) (notes 1, 2) gn package 16-lead plastic ssop 12 3 4 5 6 7 8 top view 1615 14 13 12 11 10 9 reflo v outa refcomp v outb refin/out ldac ca2scl gndv cc v outd v outc porselca0 ca1 sda t jmax = 150c, ja = 110c/w 20 19 18 17 16 6 7 8 top view 21 gnd uf package 20-lead (4mm s 4mm) plastic qfn 9 10 5 4 3 2 1 11 12 13 14 15 v outa refcomp v outb refin/out ldac dncv outd v outc porselca0 reflognd v cc dncdnc ca2scl dnc sda ca1 t jmax = 150c, ja = 37c/w exposed pad (pin 21) is gnd, must be soldered to pcb pin configuration operating temperature range ltc2655c ................................................ 0c to 70c ltc2655i .............................................C40c to 85c maximum junction temperature .......................... 150c storage temperature range ......................C65 to 150c lead temperature, gn only (soldering, 10 sec).... 300c downloaded from: http:///
ltc2655 3 2655f order information ltc2655 b c uf Cl 16 #tr pbf lead free designator tape and reel tr = tape and reel resolution 16 = 16-bit 12 = 12-bit full-scale voltage, internal reference mode l = 2.5v h = 4.096v package type uf = 20-lead (4mm 4mm) plastic qfn gn = 16-lead narrow ssop temperature grade c = commercial temperature range (0c to 70c) i = industrial temperature range (C40c to 85c) electrical grade (optional) b = 4lsb maximum inl (16-bit) product part number consult ltc marketing for information on non-standard lead based ? nish parts. consult ltc marketing for parts speci? ed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc2655 4 2655f product selection guide lead free finish tape and reel part marking* package description temperature range maximum inl ltc2655bcgn-l16#pbf ltc2655bcgn-l16#trpbf 655l16 16-lead narrow ssop 0c to 70c 4 ltc2655bign-l16#pbf ltc2655bign-l16#trpbf 655l16 16-lead narrow ssop C40c to 85c 4 ltc2655bcuf-l16#pbf ltc2655bcuf-l16#trpbf 55l16 20-lead (4mm 4mm) plastic qfn 0c to 70c 4 ltc2655biuf-l16#pbf ltc2655biuf-l16#trpbf 55l16 20-lead (4mm 4mm) plastic qfn C40c to 85c 4 ltc2655bcgn-h16#pbf ltc2655bcgn-h16#trpbf 655h16 16-lead narrow ssop 0c to 70c 4 ltc2655bign-h16#pbf ltc2655bign-h16#trpbf 655h16 16-lead narrow ssop C40c to 85c 4 ltc2655bcuf-h16#pbf ltc2655bcuf-h16#trpbf 55h16 20-lead (4mm 4mm) plastic qfn 0c to 70c 4 ltc2655biuf-h16#pbf ltc2655biuf-h16#trpbf 55h16 20-lead (4mm 4mm) plastic qfn C40c to 85c 4 ltc2655cgn-l12#pbf ltc2655cgn-l12#trpbf 655l12 16-lead narrow ssop 0c to 70c 1 ltc2655ign-l12#pbf ltc2655ign-l12#trpbf 655l12 16-lead narrow ssop C40c to 85c 1 ltc2655cuf-l12#pbf ltc2655cuf-l12#trpbf 55l12 20-lead (4mm 4mm) plastic qfn 0c to 70c 1 ltc2655iuf-l12#pbf ltc2655iuf-l12#trpbf 55l12 20-lead (4mm 4mm) plastic qfn C40c to 85c 1 ltc2655cgn-h12#pbf ltc2655cgn-h12#trpbf 655h12 16-lead narrow ssop 0c to 70c 1 ltc2655ign-h12#pbf ltc2655ign-h12#trpbf 655h12 16-lead narrow ssop C40c to 85c 1 ltc2655cuf-h12#pbf ltc2655cuf-h12#trpbf 55h12 20-lead (4mm 4mm) plastic qfn 0c to 70c 1 ltc2655iuf-h12#pbf ltc2655iuf-h12#trpbf 55h12 20-lead (4mm 4mm) plastic qfn C40c to 85c 1 consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc2655 5 2655f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2655b-l16/ ltc2655-l12 (internal reference=1.25v) symbol parameter conditions ltc2655-12 ltc2655b-16 units min typ max min typ max dc performance resolution l 12 16 bits monotonicity (note 3) l 12 16 bits dnl differential nonlinearity (note 3) l 0.1 0.5 0.3 1 lsb inl integral nonlinearity (note 3) v cc = 5.5v, v ref = 2.5v l 0.5 1 2 4 lsb load regulation v cc = 5v 10%, internal reference, mid-scale, C15ma i out 15ma l 0.04 0.125 0.6 2 lsb/ma v cc = 3v 10%, internal reference, mid-scale, C7.5ma i out 5ma l 0.06 0.25 1 4 lsb/ma zse zero-scale error l 13 13 m v v os offset error v ref = 1.25v (note 4) l 1 2 1 2 mv v os temperature coef? cient 5 5 v/c ge gain error l 0.02 0.1 0.02 0.1 %fsr gain temperature coef? cient 1 1 ppm/c symbol parameter conditions min typ max units v out dac output span internal reference external reference = v extref 0 to 2.5 0 to 2?v extref vv psr power supply rejection v cc 10% C80 db r out dc output impedance v cc = 5v 10%, internal reference, mid-scale, C15ma i out 15ma v cc = 3v 10%, internal reference, mid-scale, C7.5ma i out 7.5ma ll 0.040.04 0.150.15 ? dc crosstalk (note 5) due to full-scale output change due to load current changedue to powering down (per channel) 1.5 21 v v/ma v i sc short-circuit output current (note 6) v cc = 5.5v v extref = 2.8v code: zero-scale; forcing output to v cc code: full-scale; forcing output to gnd ll 2020 6565 mama v cc = 2.7v v extref = 1.4v code: zero-scale; forcing output to v cc code: full-scale; forcing output to gnd ll 1010 4545 mama downloaded from: http:///
ltc2655 6 2655f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2655b-l16/ltc2655-l12 (internal reference = 1.25v) symbol parameter conditions min typ max units reference reference output voltage 1.248 1.25 1.252 v reference temperature coef? cient (note 7) 2 10 ppm/c reference line regulation v cc 10% C80 db reference short-circuit current v cc = 5.5v, forcing refin/out to gnd l 35 m a refcomp pin short-circuit current v cc = 5.5v, forcing refcomp to gnd l 65 200 a reference load regulation v cc = 3v10% or 5v10%, i out = 100a sourcing 40 mv/ma reference output voltage noise density c refcomp = c refin/out = 0.1f, at f = 1khz 30 nv/ hz reference input range external reference mode (note 14) l 0.5 v cc /2 v reference input current l 0.001 1 a reference input capacitance (note 9) 20 pf power supplyv cc positive supply voltage for speci? ed performance l 2.7 5.5 v i cc supply current (note 8) v cc = 5v, internal reference on v cc = 5v, internal reference off v cc = 3v, internal reference on v cc = 3v, internal reference off ll l l 1.71.3 1.6 1.2 2.5 2 2.21.7 mama ma ma i sd supply current in shutdown mode (note 8) v cc = 5v l 3 a digital i/ov il low level input voltage (sda and scl) l 0.3v cc v v ih high level input voltage (sda and scl) l 0.7v cc v v il( ldac ) low level input voltage (ldac) v cc = 4.5v to 5.5v l 0.8 v v cc = 2.7v to 4.5v l 0.6 v v ih( ldac ) high level input voltage (ldac) v cc = 3.6v to 5.5v l 2.4 v v cc = 2.7v to 3.6v l 2v v il(ca) low level input voltage (ca0 to ca2) see test circuit 1 l 0.15v cc v v ih(ca) high level input voltage (ca0 to ca2) see test circuit 1 l 0.85v cc v r inh resistance from ca n ( n = 0,1,2) to v cc to set ca n = v cc see test circuit 2 l 10 k r inl resistance from can ( n = 0,1,2) to gnd to set ca n = gnd see test circuit 2 l 10 k r inf resistance from ca n ( n = 0,1,2) to v cc or gnd to set ca n = float see test circuit 2 l 2m v ol low level output voltage sink current =3ma l 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 13) 20+0.1c b 250 ns t sp pulse width of spikes suppressed by input filter l 05 0 n s i in input leakage 0.1v cc v in 0.9v cc l 1 a c in i/o pin capacitance (note 9) l 10 pf c b capacitance load for each bus line l 400 pf c ca n external capacitive load on address pins ca0, ca1 and ca2 l 10 pf downloaded from: http:///
ltc2655 7 2655f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2655b-h16/ltc2655-h12 (internal reference = 2.048v) symbol parameter conditions ltc2655-12 ltc2655b-16 units min typ max min typ max dc performance resolution l 12 16 bits monotonicity (note 3) l 12 16 bits dnl differential nonlinearity (note 3) l 0.1 0.5 0.3 1 lsb inl integral nonlinearity (note 3) v cc = 5.5v, v ref = 2.5v l 0.5 1 2 4 lsb load regulation v cc = 5v 10%, internal reference, mid-scale, C15ma i out 15ma l 0.04 0.125 0.6 2 lsb/ma zse zero-scale error l 13 13 m v v os offset error v ref = 2.048v (note 4) l 1 2 1 2 mv v os temperature coef? cient 5 5 v/c ge gain error l 0.02 0.1 0.02 0.1 %fsr gain temperature coef? cient 1 1 ppm/c symbol parameter conditions min typ max units v out dac output span internal reference external reference = v extref 0 to 4.096 0 to 2?v extref vv psr power supply rejection v cc 10% C80 db r out dc output impedance v cc = 5v 10%, internal reference, mid-scale, C15ma i out 15ma l 0.04 0.15 dc crosstalk due to full scale output change due to load current changedue to powering down (per channel) 1.5 21 v v/ma v i sc short-circuit output current (note 4) v cc = 5.5v v extref = 2.8v code: zero-scale; forcing output to v cc code: full-scale; forcing output to gnd ll 2020 6565 mama downloaded from: http:///
ltc2655 8 2655f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci? ed. ltc2655b-h16/ltc2655-h12 (internal reference = 2.048v) symbol parameter conditions min typ max units reference reference output voltage 2.044 2.048 2.052 v reference temperature coef? cient (note 7) 2 10 ppm/c reference line regulation v cc 10% C80 db reference short-circuit current v cc = 5.5v, forcing refin/out to gnd l 35 m a refcomp pin short-circuit current v cc = 5.5v, forcing refcomp to gnd l 65 200 a reference load regulation v cc = 5v10%, i out = 100a sourcing 40 mv/ma reference output voltage noise density c refcomp = c refin/out = 0.1f, at f = 1khz 35 nv/ hz reference input range external reference mode (note 14) l 0.5 v cc /2 v reference input current l 0.001 1 a reference input capacitance (note 9) l 20 pf power supplyv cc positive supply voltage for speci? ed performance l 4.5 5.5 v i cc supply current (note 8) v cc = 5v, internal reference on v cc = 5v, internal reference off ll 1.91.5 2.5 2 mama i sd supply current in shutdown mode (note 8) v cc = 5v l 3 a digital i/ov il low level input voltage (sda and scl) l 0.3v cc v v ih high level input voltage (sda and scl) l 0.7v cc v v il( ldac ) low level input voltage ( ldac )v cc = 4.5v to 5.5v l 0.8 v v ih( ldac ) high level input voltage ( ldac )v cc = 4.5v to 5.5v l 2.4 v v il(ca) low level input voltage (ca0 to ca2) see test circuit 1 l 0.15v cc v v ih(ca) high level input voltage (ca0 to ca2) see test circuit 1 l 0.85v cc v r inh resistance from can ( n = 0,1,2) to v cc to set ca n = v cc see test circuit 2 l 10 k r inl resistance from ca n ( n = 0,1,2) to gnd to set ca n = gnd see test circuit 2 l 10 k r inf resistance from ca n ( n = 0,1,2) to v cc or gnd to set ca n = float see test circuit 2 l 2m v ol low level output voltage sink current = 3ma l 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 13) l 20+0.1c b 250 ns t sp pulse width of spikes suppressed by input filter l 05 0 n s i in input leakage 0.1v cc v in 0.9v cc l 1 a c in i/o pin capacitance (note 9) l 10 pf c b capacitance load for each bus line l 400 pf c ca n external capacitive load on address pins ca0, ca1 and ca2 l 10 pf downloaded from: http:///
ltc2655 9 2655f electrical characteristics ltc2655b-l16/ltc2655-l12/ltc2655b-h16/ltc2655-h12 symbol parameter conditions min typ max units ac performancet s settling time ( note 10) 0.024%(1lsb at 12 bits) 0.0015%(1lsb at 16 bits) 3.99.1 ss settling time for 1lsb step 0.024%(1lsb at 12 bits) 0.0015%(1lsb at 16 bits) 2.44.5 ss voltage output slew rate 1.8 v/s capacitive load driving 1000 pf glitch impulse (note 11) at mid-scale transition, -l option 4 nv?s at mid-scale transition, -h option 7 nv?s dac to dac crosstalk (note 12) c refcomp = c refin/out = 0.22f 0.5 nv?s multiplying bandwidth 150 khz e n output voltage noise density at f = 1khz at f = 10khz 8580 nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, internal reference (-l options) 0.1hz to 10hz, internal reference (-h options)0.1hz to 200khz, internal reference (-l options) 0.1hz to 200khz, internal reference (-h options) 8 12 400450 v p-p v p-p v p-p v p-p timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v (ltc2655b-l16/ltc2655-l12), v cc = 4.5v to 5.5v (ltc2655b-h16, ltc2655-h12), v out unloaded unless otherwise speci? ed. ltc2655b-l16/ltc2655-l12/ltc2655b-h16/ltc2655-h12 (see figure 1) symbol parameter conditions min typ max units f scl scl clock frequency l 0 400 khz t hd(sta) hold time (repeated) start condition l 0.6 s t low low period of the scl clock pin l 1.3 s t high high period of the scl clock pin l 0.6 s t su(sta) set-up time for a repeated start program l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns tr rise time of both sda and scl signals (note 13) l 20+0.1c b 300 ns tf fall time of both sda and scl signals (note 13) l 20+0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s t1 falling edge of the 9th clock of the 3rd input byte to ldac high or low transition l 400 ns t2 ldac low pulse width l 20 ns the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v (ltc2655b-l16/ltc2655-l12), v cc = 4.5v to 5.5v (ltc2655b-h16, ltc2655-h12), v out unloaded unless otherwise speci? ed. downloaded from: http:///
ltc2655 10 2655f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are with respect to gnd. note 3: linearity and monotonicity are de? ned from code k l to code 2 n C1, where n is the resolution and k l is the lower end code for which no output limiting occurs. for v ref = 2.5v and n = 16, k l = 128 and linearity is de? ned from code 128 to code 65535. for v ref = 2.5v and n = 12, k l =8 and linearity is de? ned from code 8 to code 4095. note 4: inferred from measurement at code 128 (ltc2655-16), or code 8 (ltc2655-12). note 5: dc crosstalk is measured with v cc = 5v and using internal reference, with the measured dac at mid-scale.note 6: this ic includes current limiting that is intended to protect the device during momentary overload conditions. junction temperature can exceed the rated maximum during current limiting. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 7: temperature coef? cient is calculated by dividing the maximum change in output voltage by the speci? ed temperature range. maximum temperature coef? cient is guaranteed for c-grade only. note 8: digital inputs at 0v or v cc . note 9: guaranteed by design and not production tested. note 10: internal reference mode. dac is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. load is 2k in parallel with 200pf to gnd.note 11: v cc = 5v (-h options) or v cc = 3v (-l options), internal reference mode. dac is stepped 1 lsb between half-scale and half-scale C 1. load is 2k n parallel with 200pf to gnd. note 12: dac to dac crosstalk is the glitch that appears at the output of one dac due to a full scale change at the output of another dac. it is measured with v cc = 5v and using internal reference, with the measured dac at mid-scale.note 13: c b = capacitance of one bus line in pf. note 14: gain error speci? cation may be degraded for reference input voltages less than 1v. see gain error vs reference input curve in the typical performance characteristics section. electrical characteristics downloaded from: http:///
ltc2655 11 2655f dnl vs temperature refin/out output voltage vs temperature settling to 1lsb rising settling to 1lsb falling integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature code 128 inl (lsb) 43 C2C3 C1 21 0 C4 32768 49152 16384 2655 g01 65535 v cc = 3v code 128 dnl (lsb) 1.0 C0.5 0.5 0 C1.0 32768 49152 16384 2655 g02 65535 v cc = 3v temperature (c) C50 inl (lsb) 4 C2 2 31 C1C3 0 C4 50 30 10 110 90 70 C10 C30 2655 g03 130 v cc = 3v inl(pos) inl(neg) temperature (c) C50 dnl (lsb) 1.0 C0.5 0.5 0 C1.0 50 30 10 110 90 70 C30 C10 2655 g04 130 v cc = 3v dnl(pos) dnl(neg) temperature (c) C50 v ref (v) 1.2531.248 1.249 1.2521.251 1.250 1.247 50 30 10 110 90 70 C30 C10 2655 g05 130 v cc = 3v 2s/div v out 250v/div scl 3v/div 2655 g06 9th clock of 3rd data byte 7.8s 1/4 scale to 3/4 scale step v cc = 3v, v fs = 2.50v 2s/div v out 200v/div scl 3v/div 2655 g07 9th clock of 3rd data byte 7.3s 3/4 scale to 1/4 scale step v cc = 3v, v fs = 2.50v r l = 2k, c l = 200pf average of 2048 events typical performance characteristics t a = 25c unless otherwise noted. ltc2655-l16 downloaded from: http:///
ltc2655 12 2655f typical performance characteristics t a = 25c unless otherwise noted. ltc2655-h16 integral nonlinearity (inl) differential nonlinearity (dnl) code 128 inl (lsb) 4 C2 C1C3 2 31 0 C4 32768 49152 16384 2655 g08 65535 v cc = 5v code 128 dnl (lsb) 1.0 C0.5 0.5 0 C1.0 32768 49152 16384 2655 g09 65535 v cc = 5v settling to 1lsb rising settling to 1lsb falling 2s/div v out 250v/div scl 5v/div 2655 g13 9th clock of 3rd data byte 7.9s 1/4 scale to 3/4 scale step v cc = 5v, v fs = 4.096v r l = 2k, c l = 200pf 2s/div v out 250v/div scl 5v/div 2655 g14 9th clock of 3rd data byte 5.5s 3/4 scale to 1/4 scale step v cc = 5v, v fs = 4.096v r l = 2k, c l = 200pf inl vs temperature dnl vs temperature reference output voltage vs temperature temperature (c) C50 inl (lsb) 4 C2 2 31 C1C3 0 C4 50 30 10 110 90 70 C10 C30 2655 g10 130 v cc = 3v inl(pos) inl(neg) temperature (c) C50 dnl (lsb) 1.0 C0.5 0.5 0 C1.0 50 30 10 110 90 70 C30 C10 2655 g11 130 v cc = 3v dnl(pos) dnl(neg) temperature (c) C50 v ref (v) 2.0542.044 2.046 2.0522.050 2.048 2.042 50 30 10 110 90 70 C30 C10 2655 g12 130 v cc = 5v downloaded from: http:///
ltc2655 13 2655f typical performance characteristics current limiting headroom at rails vs output current offset error vs temperature integral nonlinearity (inl) differential nonlinearity (inl) settling to 1lsb falling load regulation code 8 inl (lsb) 1.0 C0.5 0.5 0 C1.0 2048 3072 1024 2655 g15 4095 v cc = 5v v ref = 2.048v code 8 dnl (lsb) 1.0 C0.5 0.5 0 C1.0 2048 3072 1024 2655 g16 4095 v cc = 3v v ref = 1.25v 2s/div v out 1mv/div scl 3v/div 2655 g17 4.0s 3/4 to 1/4 scale stepv cc = 3v, v fs = 2.5v r l = 2k, c l = 200pf average of 2048 events i out (ma) C50 $ v out (mv) 10C6 C8 C4 C2 86 4 2 0 C10 0 C10 C20 30 40 20 10 C40 C30 2655 g18 50 internal ref code = mid-scale v cc = 5v (ltc2655-h) v cc = 3v (ltc2655-l) i out (ma) C50 v out (v) 0.20 C0.10C0.15 C0.05 0.150.10 0.05 0 C0.20 0 C10 C20 30 40 20 10 C40 C30 2655 g19 50 internal ref code = mid-scale v cc = 5v (ltc2655-h) v cc = 3v (ltc2655-l) i out (ma) 0 v out (v) 5.01.0 0.5 1.5 2.0 4.54.0 3.5 3.0 2.5 0 5 4 38 9 7 6 12 2655 g20 10 5v (ltc2655-h) sourcing 3v (ltc2655-l) sourcing 5v (ltc2655-h) sinking 3v (ltc2655-l) sinking temperature (c) C50 offset error (mv) 3 C2 C1 21 0 C3 50 30 10 110 90 70 C30 C10 2655 g21 130 t a = 25c unless otherwise noted. ltc2655-12 ltc2655 zero-scale error vs temperature gain error vs temperature temperature (c) C50 zero-scale error (mv) 3.02.0 0.5 2.51.5 1.0 0 50 30 10 110 90 70 C30 C10 2655 g22 130 temperature (c) C50 gain error (lsb) 6432 16 C48 48 0 C32 C16C64 50 30 10 110 90 70 C30 C10 2655 g23 130 ltc2655-16 downloaded from: http:///
ltc2655 14 2655f typical performance characteristics offset error vs reference input reference voltage (v) 0.5 offset error (mv) 2.0 C1.0C1.5 C0.5 1.51.0 0.5 0 C2 2 1 1.5 2655 g24 2.5 v cc = 5v offset error of 4 channels t a = 25c unless otherwise noted. ltc2655 supply current vs temperature i cc shutdown vs temperature multiplying bandwidth temperature (c) C50 supply current (ma) 3.02.0 2.51.5 1.0 50 30 10 110 90 70 C30 C10 2655 g28 130 ltc2655-h v cc = 5v, code = ms internal reference ltc2655-l v cc = 3v, code = ms internal reference temperature (c) C50 i cc shutdown (a) 53 42 1 0 50 30 10 110 90 70 C30 C10 2655 g29 130 ltc2655-h v cc = 5v ltc2655-l v cc = 3v frequency (hz) amplitude (db) 2655 g30 82 0 4 6 C2C4 C6 C8 C10C12 1k 100k 1m 10k v s = 5v v ref(dc) = 2v v ref(ac) = 0.2v p-p code = full-scale gain error vs reference input i cc shutdown vs v cc supply current vs logic voltage reference voltage (v) 0.5 gain error (lsb) 64 C32C48 C16 4832 16 0 C64 2 1 1.5 2655 g25 2.5 ltc2655-16 v cc = 5.5v gain error of 4 channels v cc (v) 2.5 i cc (na) 450150 100 50 200 400350 300 250 0 5 3.5 3 4.5 4 2655 g26 5.5 logic voltage (v) 0 i cc (ma) 2.61.6 2.42.2 2.0 1.8 1.4 2 14 3 2655 g27 sweep scl and sda between 0v and v cc v cc = 3v (ltc2655-l) v cc = 5v (ltc2655-h) 5 large-signal response mid-scale glitch impulse 2s/div v out 1v/div 2655 g31 v cc = 5v, v ref = 2.048v zero-scale to full-scale 2s/div v out 5mv/div scl 5v/div 2655 g32 ltc2655-h16, v cc = 5v 7nv-s typ ltc2655-l16, v cc = 3v 4nv-s typ 9th clock of 3rd data byte downloaded from: http:///
ltc2655 15 2655f typical performance characteristics dac output 0.1hz to 10hz voltage noise reference 0.1hz to 10hz voltage noise dac to dac crosstalk (dynamic) power-on reset glitch power-on reset to mid-scale noise voltage vs frequency 2s/div v out 0.5mv/div one dac switch 0-fs 1v/div 2655 g33 ltc2655-l16, v cc = 5v, 0.4nv?s typ c refcomp = c refout = 0.22f 200s/div v out 10mv/div v cc 2v/div 2655 g34 zero-scale 1ms/div v out 1v/div v cc 2v/div 2655 g35 ltc2655-l frequency (hz) noise voltage (nv/ hz ) 2655 g36 400300 200 100 0 10 100 100k 1m 10k 1k v cc = 5v code = mid-scaleinternal ref c refcomp = c refout = 0.1f ltc2655-h ltc2655-l 1s/div 5v/div 2655 g37 v cc = 5v, ltc2655-h code = mid-scaleinternal ref c refcomp = c refout = 0.1f 1s/div 2v/div 2655 g38 v refout = 2.048v c refcomp = c refout = 0.1f t a = 25c unless otherwise noted. ltc2655 downloaded from: http:///
ltc2655 16 2655f pin functions reflo (pin 1/pin 20): reference low. the voltage at this pin sets the zero-scale voltage of all dacs. this pin should be tied to gnd. v outa to v outd (pins 2,4,13,14/pins 1, 3, 13, 14): dac analog voltage outputs. the output range is 0v to 2 times the voltage at the refin/out pin. refcomp (pin 3/pin 2): internal reference compensation. for low noise and reference stability, tie 0.1f capacitor to gnd. connect to gnd to use an external reference at start-up. command 0111b must still be issued to turn off internal reference. refin/out (pin 5/pin 4): this pin acts as the internal reference output in internal reference mode and acts as the reference input pin in external reference mode. when acting as an output the nominal voltage at this pin is 1.25v for -l options and 2.048v for -h options. for low noise and reference stability tie a capacitor from this pin to gnd. capacitor value must be c refcomp . in external reference mode, the allowable reference input voltage range is 0.5v to v cc /2. ldac (pin 6/pin 5): asynchronous dac update. a fall- ing edge on this input after four bytes have been written into the part, immediately updates the dac register with the contents of the input register. a low on this input without a complete 32-bit (four bytes including the slave address) data write transfer to the part does not update the dac output. software power-down is disabled when ldac is low. ca2 (pin 7/pin 6): chip address bit 2. tie this pin to v cc , gnd or leave it ? oating to select an i 2 c slave address for the part (table 2). scl (pin 8/pin 7): serial clock input. data is shifted into the sda pin at the rising edges of the clock. this high impedance pin requires a pull-up resistor or current source to v cc . sda (pin 9/pin 9): serial data bidirectional. data is shifted into the sda pin and acknowledged by the sda pin. this is a high impedance pin while data is shifted in. it is an open- drain n-channel output during acknowledgement. this pin requires a pull-up resistor or current source to v cc . ca1 (pin 10/pin 10): chip address bit 1. tie this pin to v cc , gnd or leave it ? oating to select an i 2 c slave address for the part (table 2). ca0 (pin 11/pin 11): chip address bit 0. tie this pin to v cc , gnd or leave it ? oating to select an i 2 c slave address for the part (table 2). porsel (pin 12/pin 12): power-on-reset select. if tied to gnd, the part resets to zero-scale at power-up, if tied to v cc , the part resets to mid-scale. v cc (pin 15/pin 18): supply voltage input. for -l options, 2.7v v cc 5.5v, and for -h options, 4.5v v cc 5.5v. bypass to ground with a 0.1f capacitor placed as close to pin as possible. gnd (pin 16/pin 19, exposed pad pin 21): ground. must be soldered to pcb ground. dnc (na/pins 8, 15, 16, 17): do not connect these pins. (gn/uf) downloaded from: http:///
ltc2655 17 2655f block diagram 2655 bd gndv outa v outb scl ca2ldac reflo ca1 ca0 refin/out refcomp v cc v outd v outc porsel sda internal reference dac a power-on reset dac b dac d dac c register 32-bit shift register 2-wire interface register register register register register register register downloaded from: http:///
ltc2655 18 2655f timing diagram figure 1 v ih(ca n ) /v il(ca n ) can 100 2655 tc01 gnd r inh /r inl /r inf v dd 2655 tc02 test circuit 1 test circuit 2 test circuits sda t f s t r t low t hd(sta) all voltage levels refer to v ih(min) and v il(max) levels t hd(dat) t su(dat) t su(sta) t hd(sta) t su(sto) t sp t buf t r t f t high scl s p s 2655 f01 9th clock of 3rd data byte t 1 scl ldac downloaded from: http:///
ltc2655 19 2655f the ltc2655 is a family of quad voltage output dacs in 20-lead 4mm 4mm qfn and in 16-lead narrow ssop packages. each dac can operate rail-to-rail in external reference mode, or with its full-scale voltage set by an integrated reference. four combinations of accuracy (16-bit and 12-bit), and full-scale voltage (2.5v or 4.096v) are available. the ltc2655 is controlled using a 2-wire i 2 c compatible interface. power-on reset the ltc2655-l/ltc2655-h clear the output to zero-scale if porsel pin is tied to gnd, when power is ? rst applied, making system initialization consistent and repeatable. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2655 contains circuitry to reduce the power-on glitch. the analog outputs typically rise less than 10mv above zero-scale during power on if the power supply is ramped to 5v in 1ms or more. in general, the glitch amplitude decreases as the power supply ramp time is increased. see power-on reset glitch in the typical performance characteristics section. alternatively, if porsel pin is tied to v cc , the ltc2655-l/ ltc2655-h set the output to mid-scale when power is ? rst applied. power supply sequencing and start-up for the ltc2655 family of parts, the internal reference is powered up at start-up by default. if an external reference is to be used, refcomp (pin 3/pin 2, gn/uf) must be hardwired to gnd. this con? guration allows the use of an external reference at start-up and converts the refin/out pin to an input. however, the internal reference will still be on and draw supply current. in order to use an external reference, command 0111b should be used to turn the internal reference off (see table 1). the voltage at refin/out (pin 5/pin 4, gn/uf) should be kept within the range C 0.3v refin/out v cc + 0.3v (see the absolute maximum ratings section). particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at v cc (pin 15/pin 18, gn/uf) is in transition. transfer function the digital-to-analog transfer function is v out(ideal) = 2 ? k/2 n [v ref C reflo] + reflo where k is the decimal equivalent of the binary dac input code, n is the resolution, and v ref is the voltage at the refin/out pin. the resulting dac output span is 0v to 2?v ref , as it is necessary to tie reflo to gnd. v ref is nominally 1.25v for ltc2655-l and 2.048v for ltc2655-h, in internal reference mode. table 1 command* c3 c2 c1 c0 0 0 0 0 write to input register n 0 0 0 1 update (power-up) dac register n 0 0 1 0 write to input register n , update (power-up) all 0 0 1 1 write to and update (power-up) n 0 1 0 0 power-down n 0 1 0 1 power-down chip (all dacs and reference) 0 1 1 0 select internal reference (power-up reference) 0 1 1 1 select external reference (power-down reference) 1 1 1 1 no operation address ( n )* a3 a2 a1 a0 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d 1 1 1 1 all dacs * command and address codes not shown are reserved and should not be used. serial interface the ltc2655 communicates with a host using the stan- dard 2-wire i 2 c interface. the timing diagram (figure 1) shows the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the value of these pull-up resistors is dependent on the power supply and can be obtained from the i 2 c speci? cations. for an i 2 c bus operating in the fast mode, an active pull-up will be operation downloaded from: http:///
ltc2655 20 2655f necessary if the bus capacitance is greater than 200pf. the ltc2655 is a receive-only (slave) device. the master can write to the ltc2655. the ltc2655 does not respond to a read command from the master. the start (s) and stop (p) conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a communication to a slave device by transmitting a start condition (see figure 1). a start condition is generated by transitioning sda from high to low while scl is high. when the master has ? nished communicating with the slave, it issues a stop condition. a stop condition is generated by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. acknowledgethe acknowledge signal is used for handshaking between the master and the slave. an acknowledge (active low) generated by the slave lets the master know that the lat- est byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line (high) during the acknowledge clock pulse. the slave-receiver must pull down the sda bus line during the acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. the ltc2655 responds to a write by a master in this manner. the ltc2655 does not acknowledge a read (retains sda high during the period of the acknowledge clock pulse). chip address the state of ca0, ca1 and ca2 decides the slave address of the part. the pins ca0, ca1 and ca2 can be each set to any one of three states: v cc , gnd or ? oat. this results in 27 selectable addresses for the part. the slave address assignments are shown in table 2. in addition to the address selected by the address pins, the parts also respond to a global address. this address allows a common write to all ltc2655 parts to be accom- plished with one 3-byte write transaction on the i 2 c bus. the global address is a 7-bit on-chip hardwired address and is not selectable by ca0, ca1 and ca2. the addresses corresponding to the states of ca0, ca1 and ca2 and the global address are shown in table 2. the maximum capacitive load allowed on the address pins (ca0, ca1 and ca2) is 10pf, as these pins are driven during address detection to determine if they are ? oating. table 2. slave address map ca2 ca1 ca0 a6 a5 a4 a3 a2 a1 a0 gnd gnd gnd 0 0 1 0 0 0 0 gnd gnd float 0 0 1 0 0 0 1 gnd gnd v cc 0010010 gnd float gnd 0 0 1 0 0 1 1 gnd float float 0 1 0 0 0 0 0 gnd float v cc 0100001 gnd v cc gnd 0 1 0 0 0 1 0 gnd v cc float 0 1 0 0 0 1 1 gnd v cc v cc 0110000 float gnd gnd 0 1 1 0 0 0 1 float gnd float 0 1 1 0 0 1 0 float gnd v cc 0110011 float float gnd 1 0 0 0 0 0 0 float float float 1 0 0 0 0 0 1 float float v cc 1000010 float v cc gnd 1 0 0 0 0 1 1 float v cc float 1 0 1 0 0 0 0 float v cc v cc 1010001 v cc gnd gnd 1 0 1 0 0 1 0 v cc gnd float 1 0 1 0 0 1 1 v cc gnd v cc 1100000 v cc float gnd 1 1 0 0 0 0 1 v cc float float 1 1 0 0 0 1 0 v cc float v cc 1100011 v cc v cc gnd 1 1 1 0 0 0 0 v cc v cc float 1 1 1 0 0 0 1 v cc v cc v cc 1110010 global address 1 1 1 0 0 1 1 operation downloaded from: http:///
ltc2655 21 2655f operation write word protocol the master initiates communication with the ltc2655 with a start condition and a 7-bit slave address followed by the write bit (w) = 0. the ltc2655 acknowledges by pulling the sda pin low at the 9th clock if the 7-bit slave address matches the address of the part (set by ca0, ca1 and ca2) or the global address. the master then transmits three bytes of write data. the ltc2655 acknowledges each byte of data by pulling the sda line low at the 9th clock of each data byte transmission. after receiving three com- plete bytes of data, the ltc2655 executes the command speci? ed in the 24-bit input word. if more than three data bytes are transmitted after a valid 7-bit slave address, the ltc2655 does not acknowledge the extra bytes of data (sda is high during the 9th clock). the ? rst byte of the input word consists of the 4-bit command followed by the 4-bit address. the next two bytes consist of the 16-bit data word. the 16-bit data word consists of the 16-bit, or 12-bit input code, msb to lsb, followed by 0 or 4 dont care bits (ltc2655-16 and ltc2655-12 respectively). a typical ltc2655 write transaction is shown in figure 2. the command (c3-c0) and address (a3-a0) assignments are shown in table 1. the ? rst four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32-bit shift register into the input register. in an update operation, the data word is copied from the input register to the dac register and converted to an analog voltage at the dac output. the update operation also powers up the dac if it had been in power-down mode. the data path and registers are shown in the block diagram. power-down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four outputs are needed. when in power-down, the buffer ampli? ers, bias circuits and integrated reference circuits are disabled, and draw essentially zero current. the dac outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 80k resistors. input- and dac-register contents are not disturbed during power-down. any channel or combination of channels can be put into power-down mode by using command 0100b in combina- tion with the appropriate dac address, ( n ). the integrated reference is automatically powered down when external reference mode is selected using command 0111b. in ad- dition, all the dac channels and the integrated reference together can be put into power-down mode using the power-down chip command 0101b. for all power-down commands the 16-bit data word is ignored, but still required in order to complete a full communication cycle. normal operation resumes by executing any command which includes a dac update, in software as shown in table 1 or using the asynchronous ldac pin. the selected dac is powered up as its voltage output is updated. when a dac which is in a powered-down state is powered up and updated, normal settling is delayed. if less than four dacs are in a powered-down state prior to the update command, the power-up delay time is approximately 12s. if on the other hand, all four dacs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual dac ampli? ers and the integrated reference. downloaded from: http:///
ltc2655 22 2655f in this case, the power-up delay time is approximately 14s. the power-up of the integrated reference depends on the command that powered it down. if the reference is powered down using the select external reference com- mand (0111b), then it can only be powered back up by sending the select internal reference command (0110b). however if the reference was powered down by sending the power-down chip command (0101b), then in addition to the select internal reference command (0110b), any command that powers up the dacs will also power-up the integrated reference. reference modes for applications where an accurate external reference is not available, the ltc2655 has a user-selectable, inte- grated reference. the ltc2655-l has a 1.25v reference that provides a full-scale output of 2.5v. the ltc2655-h has a 2.048v reference that provides a full-scale output of 4.096v. both references exhibit a typical temperature drift of 2ppm/c. internal reference mode can be selected by using command 0110b, and is the power-on default. a buffer is needed if the internal reference is required to drive external circuitry. for reference stability and low noise, it is recommended that a 0.1f capacitor be tied between refcomp and gnd. in this con? guration, the internal reference can drive up to 0.1f capacitive load without any stability problems. in order to ensure stable operation, the capacitive load on the refin/out pin should not exceed the capacitive load on the refcomp pin. the dac can also operate in external reference mode using command 0111b. in this mode, the refin/out pin acts as an input that sets the dacs reference voltage. this input is high impedance and does not load the external reference source. the acceptable voltage range at this pin is 0.5v refin/out v cc /2. the resulting full-scale output voltage is 2?v refin/out . for using external refer- ence at start-up, see the power supply sequencing and start-up sections. integrated reference buffers each of the four dacs in ltc2655 has its own integrated high performance reference buffer. the buffers have very high input impedance and do not load the reference volt- age source. these buffers shield the reference voltage from glitches caused by dac switching and thus minimize dac-to-dac dynamic crosstalk. by tying 0.22f capacitors between refcomp and gnd, and also between refin/out and gnd, the crosstalk can be reduced to less than 1nv?s. see the curve dac-to-dac crosstalk (dynamic) in the typical performance characteristics section. voltage outputs each of the four rail-to-rail ampli? ers contained in ltc2655 has guaranteed load regulation when sourcing or sinking up to 15ma at 5v (7.5ma at 3v). load regulation is a measure of the ampli? ers ability to maintain the rated voltage accuracy over a wide range of load conditions. the measured change in output voltage per milliampere of forced load current change is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the ampli? ers dc output impedance is 0.040 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30 typical channel resistance of the output devices; e.g., when sinking 1ma, the minimum output voltage = 30 ? 1ma = 30mv. see the graph headroom at rails vs output current in the typical performance characteristics section. the ampli? ers are stable driving capacitive loads of up to 1000pf. operation downloaded from: http:///
ltc2655 23 2655f board layout the excellent load regulation and dc crosstalk performance of these devices is achieved in part by keeping signal and power grounds separate. the pc board should have separate areas for the analog and digital sections of the circuit. this keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the devices ground pin as possible. ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. the gnd pin functions as a return path for power supply currents in the device and should be connected to analog ground. the reflo pin should be connected to system star ground. resistance from the reflo pin to system star ground should be as low as possible. rail-to-rail output considerationsin any rail-to-rail voltage output device, the output is limited to voltages within the supply range. since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in figure 3b. similarly, limiting can occur in external refer- ence mode near full scale when the refin/out pin is at v cc /2. if v refin/out = v cc /2 and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc as shown in figure 3c. no full-scale limiting can occur if v refin/out (v cc C f se )/2. offset and linearity are de? ned and tested over the region of the dac transfer function where no output limiting can occur. operation downloaded from: http:///
ltc2655 24 2655f operation figure 2. typical ltc2655 input waveformprogramming dac output for full-scale ack ack 123456789123456789123456789123456789 2655 f02 ack start stop full-scale voltage zero-scale voltage sda sa6 sa5 sa4 sa3 sa2 sa1 sa0 scl v out c2 c3 c3 c2 c1 c0 a3 a2 a1 a0 c1 c0 a3 a2 a1 a0 ack command d15 d14 d13 d12 d11 d10 d9 d8 ms data d7 d6 d5 d4 d3 d2 d1 d0 ls data sa6 sa5 sa4 sa3 sa2 sa1 sa0 wr slave address downloaded from: http:///
ltc2655 25 2655f operation 2655 f03 input code (b) output voltage negative offset 0v 32, 768 0 65, 535 input code output voltage (a) v ref = v cc v ref = v cc (c) input code outputvoltage positivefse figure 3. effects of rail-to-rail operation on a dac transfer curve. (a) overall transfer function, (b) effect of negative offset for codes near zero-scale, (c) effect of positive full-scale error for codes near full-scale downloaded from: http:///
ltc2655 26 2655f package description gn package 16-lead plastic ssop (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note:1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale downloaded from: http:///
ltc2655 27 2655f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uf package 20-lead (4mm 4mm) plastic qfn (reference ltc dwg # 05-08-1710 rev a) 4.00 0.10 4.00 0.10 note:1. drawing is proposed to be made a jedec package outline mo-220 variation (wggd-1)?o be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 20 19 12 bottom view?xposed pad 2.00 ref 2.45 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ?0.05 (uf20) qfn 01-07 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.00 ref 2.45 0.05 3.10 0.05 4.50 0.05 package outline pin 1 notchr = 0.20 typ or 0.35 45 chamfer 2.45 0.10 2.45 0.05 downloaded from: http:///
ltc2655 28 2655f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0710 printed in usa related parts typical application part number description comments ltc2609/ltc2619/ ltc2629 quad 16-/14-/12-bit i 2 c v out dacs 250a per dac, 2.7v to 5.5v supply range, rail-to-rail output with separate v ref pins for each dac, ssop-16 package ltc2605/ltc2615/ ltc2625 octal 16-/14-/12-bit i 2 c v out dacs 250a per dac, 2.7v to 5.5v supply range, rail-to-rail output, ssop-16 package ltc2607/ltc2617/ ltc2627 dual 16-/14-/12-bit i 2 c v out dacs 260a per dac, 2.7v to 5.5v supply range, rail-to-rail output, 3mm 4mm dfn-12 package ltc2606/ltc2616/ ltc2626 single 16-/14-/12-bit i 2 c v out dacs 270a per dac, 2.7v to 5.5v supply range, rail-to-rail output, 3mm 3mm dfn-10 package ltc2654 quad 16-/12-bit spi v out dacs with 10ppm/c (max) reference 4lsb inl, 1lsb dnl, 4mm 4mm qfn-20, narrow ssop-16 packages ltc2656/ltc2657 octal 16-/12-bit spi/i 2 c v out dacs with 10ppm/c (max) reference 4lsb inl, 1lsb dnl, 4mm 5mm qfn-20, tssop-20 packages ltc2634/ltc2635 quad 12-/10-/8-bit spi/i 2 c v out dacs with 10ppm/c (typ) reference 125a per dac, 2.7v to 5.5v supply range, rail-to-rail output, 3mm 3mm qfn-16 and msop-10 packages ltc2636/ltc2637 octal 12-/10-/8-bit spi/i 2 c v out dacs with 10ppm/c (typ) reference 125a per dac, 2.7v to 5.5v supply range, rail-to-rail output, 4mm 3mm dfn-14 and msop-16 packages ltc2630/ltc2631 single 12-/10-/8-bit spi/i 2 c v out dacs with bidirectional 10ppm/c (typ) reference 180a per dac, 2.7v to 5.5v supply range, rail-to-rail output, 6-lead sc70 package (ltc2630), 8-lead tsot-23 (ltc2631) ltc2641/ltc2642 single 16-/14-/12-bit spi v out dacs with 1lsb inl, dnl 1lsb (max) inl, dnl, 120a, 3mm 3mm dfn and msop packages ltc1669 10-bit i 2 c interface v out micropower dac 60a, 0.75 lsb dnl, rail-to-rail, 5-lead sot-23 and msop-8 packages ltc6240 single 18mhz, cmos op amp low noise, rail-to-rail lt1991 precision gain selectable difference ampli? er 100a micropower, pin selectable gain = C13 to 14 2655 ta02 ldac gnd gnd reflo ltc2655iuf-l16* porsel 5v *pin numbers shown are for the qfn package. v cc refcomp refin/out dnc dnc dnc dnc sclsda ca0 ca1 ca2 79 1110 6 518 1716 24 to microcontroller v outa v outb v outc v outd 13 13 14 m9m3 m1 89 10 12 3 p1p3 p9 +5v c1 0.1f c3 0.1f c2 0.1f +C 450k 150k 150k 450k 50k 50k 450k 4pf 450k v out 5v 6 45 7 4pf C12v +12v lt1991 C + ltc6240is5 +5v 19 21 20 12 8 15 34 52 1 v cc v ee ref 5v bipolar output dac downloaded from: http:///

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